1. Technical Field
The present disclosure relates to a semiconductor element, and more particularly to a silicon carbide semiconductor element such as a power semiconductor device used for high breakdown voltage and large current, and a method for manufacturing the silicon carbide semiconductor element.
2. Description of the Related Art
Silicon carbide (SiC) is a high-hardness semiconductor material having a band gap larger than that of silicon (Si), and is applied to various semiconductor devices such as a power element, an environmentally-resistant element, a high-temperature operation element, and a high-frequency element. Among these elements, application to power elements, such as a semiconductor element and a rectifier element, is gaining attention. Power elements using SiC have an advantage that they can significantly reduce power loss, compared to power elements using Si. In addition, by utilizing such properties, SiC power elements can implement a more compact semiconductor device as compared to Si power elements.
A field effect transistor (FET) having a metal-oxide-semiconductor (MOS) structure is a typical semiconductor element among various power elements that use SiC. In this description, an FET having a MOS structure is referred to as a “MOSFET”.
A semiconductor element using SiC is expected to implement high breakdown voltage and to reduce a loss when the semiconductor element is energized. In addition, MOSFET is a majority carrier device, and enables a unipolar operation, and thus, is expected to serve as a high-speed switching element. Therefore, a MOSFET using SiC (hereinafter referred to as “SiC-MOSFET”) is demanded to reduce conduction loss and switching loss simultaneously.
For example, a configuration disclosed in PTL 1 has been known as a conventional configuration to reduce conduction loss (particularly, see FIG. 1 in PTL 1). In the configuration disclosed in PTL 1, a high-concentration n-type epitaxial layer is formed on a low-concentration n-type drift, layer, and the n-type epitaxial layer is used as a channel layer. The configuration having the channel layer enables the flow of carriers to keep away from an interface of a gate insulating film. Accordingly, this configuration can prevent scattering of carriers with defects near the interface, thereby being capable of increasing field-effect mobility, and thus, being capable of reducing conduction loss of the semiconductor element.
On the other hand, an increase in a switching speed is effective to reduce switching loss. However, to increase the switching speed, it is necessary to reduce gate resistance and to reduce various capacitive components such as input capacitance or feedback capacitance. Among these various capacitive components, in particular, feedback capacitance, that is, gate-drain capacitance, most largely contributes to switching loss. Therefore, the reduction in the gate-drain capacitance is inevitable to ensure a high-speed operation with less loss.
For example, a configuration disclosed in PTL 2 has been known as a conventional configuration to reduce gate-drain capacitance. FIGS. 2 and 3 in PTL 2 are cross-sectional views illustrating a vertical MOSFET having a conventional configuration, wherein a gate electrode is removed from a part of a portion on a junction field effect transistor (JFET) region interposed between p-type body regions. According to this configuration, the area where the gate electrode and the JFET region overlap each other is reduced in a planar view, whereby the gate-drain capacitance can be reduced. The configuration having the above features is also applied to a semiconductor element using SiC.